MPC565 Reference Manual
Additional Devices Supported:
MPC566
MPC565RM
REV 2.2
11/2005
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MPC565RM
REV 2.2
11/2005
Contents
Paragraph
Number
Title
Page
Number
About This Book
Audience ...................................................................................................................... xxxix
Organization................................................................................................................. xxxix
Suggested Reading............................................................................................................ xli
Conventions and Nomenclature....................................................................................... xlii
Notational Conventions .................................................................................................. xliii
Acronyms and Abbreviations ......................................................................................... xliv
References........................................................................................................................ xlv
Chapter 1
Overview
1.1
1.2
1.3
1.3.1
1.3.2
1.3.3
1.3.4
1.3.5
1.3.6
1.3.7
1.3.8
1.3.9
1.3.10
1.3.10.1
1.3.10.2
1.3.11
1.3.11.1
1.3.11.2
1.3.12
1.3.13
1.3.14
1.4
1.5
1.6
1.7
1.8
1.9
Introduction ..................................................................................................................... 1-1
Block Diagram ................................................................................................................ 1-2
Detailed Feature List ....................................................................................................... 1-3
High Performance CPU System ................................................................................. 1-3
RISC MCU Central Processing Unit (RCPU) ............................................................ 1-3
MPC500 System Interface (USIU) ............................................................................. 1-4
Burst Buffer Controller (BBC) Module ...................................................................... 1-4
Flexible Memory Protection Unit ............................................................................... 1-4
Memory Controller ..................................................................................................... 1-5
1 Mbyte of CDR3 Flash EEPROM Memory (UC3F) ................................................ 1-5
36-Kbyte Static RAM (CALRAM) ............................................................................ 1-5
General Purpose I/O Support (GPIO) ......................................................................... 1-5
Debug Features ........................................................................................................... 1-6
Nexus Debug Port (Class 3) ................................................................................... 1-6
Data Link Controller (DLCMD2) Module ............................................................. 1-6
Integrated I/O System ................................................................................................. 1-7
Time Processor Units (TPU3) ................................................................................ 1-7
22-Channel Modular I/O System (MIOS14) .......................................................... 1-7
Two Enhanced Queued Analog-to-Digital Converter Modules (QADC64E) ............ 1-7
Three CAN 2.0B Controller (TouCAN) Modules ...................................................... 1-8
Queued Serial Multi-Channel Modules (QSMCM) .................................................... 1-8
MPC565 Optional Features ............................................................................................ 1-9
Differences between the MPC565 and the MPC555 ...................................................... 1-9
Additional MPC565 Differences .................................................................................. 1-10
SRAM Keep-Alive Power Behavior ............................................................................. 1-11
MPC565 Memory Map ................................................................................................. 1-11
MPC565 Pinout Diagram .............................................................................................. 1-14
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iii
Contents
Paragraph
Number
Title
Page
Number
Chapter 2
Signal Descriptions
2.1
2.2
2.2.1
2.3
2.4
2.4.1
2.4.2
2.5
2.5.1
2.5.2
2.5.3
2.5.4
2.5.4.1
2.5.4.2
2.5.4.3
2.5.4.4
2.5.5
Signal Groupings ............................................................................................................ 2-1
Signal Summary .............................................................................................................. 2-3
MPC565 Signal Multiplexing ................................................................................... 2-22
Pad Module Configuration Register (PDMCR) ............................................................ 2-22
Pad Module Configuration Register (PDMCR2) .......................................................... 2-24
JTAG / BDM ............................................................................................................ 2-25
QSMCM and DLCMD2 (J1850) Modules ............................................................... 2-25
Reset State ..................................................................................................................... 2-26
Signal Functionality Configuration Out of Reset ..................................................... 2-26
Signal State During Reset ......................................................................................... 2-26
Power-On Reset and Hard Reset .............................................................................. 2-27
Pull-Up/Pull-Down ................................................................................................... 2-27
Pull-Up/Pull-Down Enable and Disable for 5-V Only and 2.6-V Only Signals .. 2-27
Pull-Down Enable and Disable for 5-V/2.6-V Multiplexed Signals .................... 2-27
Special Pull Resistor Disable Control Functionality (SPRDS) ............................ 2-27
Pull Device Select (PULL_SEL) .......................................................................... 2-27
Signal Reset States .................................................................................................... 2-28
Chapter 3
Central Processing Unit
3.1
3.2
3.3
3.4
3.4.1
3.4.2
3.4.3
3.4.4
3.5
3.6
3.7
3.7.1
3.7.2
3.7.3
3.7.4
3.7.4.1
3.7.4.2
RCPU Block Diagram .................................................................................................... 3-1
RCPU Key Features ........................................................................................................ 3-3
Instruction Sequencer ..................................................................................................... 3-3
Independent Execution Units .......................................................................................... 3-4
Branch Processing Unit (BPU) ................................................................................... 3-5
Integer Unit (IU) ......................................................................................................... 3-5
Load/Store Unit (LSU) ............................................................................................... 3-6
Floating-Point Unit (FPU) .......................................................................................... 3-6
Levels of the PowerPC ISA Architecture ....................................................................... 3-6
RCPU Programming Model ............................................................................................ 3-7
User Instruction Set Architecture (UISA) Register Set ................................................ 3-12
General-Purpose Registers (GPRs) ........................................................................... 3-12
Floating-Point Registers (FPRs) ............................................................................... 3-12
Floating-Point Status and Control Register (FPSCR) .............................................. 3-13
Condition Register (CR) ........................................................................................... 3-16
Condition Register CR0 Field Definition ............................................................. 3-17
Condition Register CR1 Field Definition ............................................................. 3-17
MPC565 Reference Manual, REV 2.2
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iv
Contents
Paragraph
Number
3.7.4.3
3.7.5
3.7.6
3.7.7
3.8
3.9
3.9.1
3.9.2
3.9.3
3.9.4
3.9.5
3.9.6
3.9.7
3.9.8
3.9.9
3.9.10
3.9.10.1
3.9.10.2
3.9.10.3
3.10
3.10.1
3.10.2
3.10.3
3.11
3.11.1
3.11.2
3.11.3
3.11.4
3.11.5
3.12
3.13
3.13.1
3.13.2
3.13.3
3.13.4
3.13.5
3.13.6
3.13.7
3.13.7.1
3.13.7.2
3.13.8
Title
Page
Number
Condition Register CRn Field — Compare Instruction ....................................... 3-17
Integer Exception Register (XER) ............................................................................ 3-18
Link Register (LR) .................................................................................................... 3-19
Count Register (CTR) ............................................................................................... 3-19
VEA Register Set — Time Base (TB) .......................................................................... 3-20
OEA Register Set .......................................................................................................... 3-20
Machine State Register (MSR) ................................................................................. 3-20
DAE/Source Instruction Service Register (DSISR) ................................................. 3-22
Data Address Register (DAR) .................................................................................. 3-23
Time Base Facility (TB) — OEA ............................................................................. 3-23
Decrementer Register (DEC) .................................................................................... 3-23
Machine Status Save/Restore Register 0 (SRR0) ..................................................... 3-23
Machine Status Save/Restore Register 1 (SRR1) ..................................................... 3-23
General SPRs (SPRG0–SPRG3) .............................................................................. 3-24
Processor Version Register (PVR) ........................................................................... 3-25
Implementation-Specific SPRs ................................................................................. 3-25
EIE, EID, and NRI Special-Purpose Registers ..................................................... 3-25
Floating-Point Exception Cause Register (FPECR) ............................................. 3-26
Additional Implementation-Specific Registers ..................................................... 3-26
Instruction Set ............................................................................................................... 3-27
Instruction Set Summary .......................................................................................... 3-28
Recommended Simplified Mnemonics ..................................................................... 3-33
Calculating Effective Addresses ............................................................................... 3-34
Exception Model ........................................................................................................... 3-34
Exception Classes ..................................................................................................... 3-35
Ordered Exceptions ................................................................................................... 3-35
Unordered Exceptions ............................................................................................... 3-35
Precise Exceptions .................................................................................................... 3-36
Exception Vector Table ............................................................................................ 3-36
Instruction Timing ........................................................................................................ 3-37
User Instruction Set Architecture (UISA) .................................................................... 3-39
Computation Modes .................................................................................................. 3-39
Reserved Fields ......................................................................................................... 3-39
Classes of Instructions .............................................................................................. 3-39
Exceptions ................................................................................................................. 3-40
Branch Processor ...................................................................................................... 3-40
Instruction Fetching .................................................................................................. 3-40
Branch Instructions ................................................................................................... 3-40
Invalid Branch Instruction Forms ......................................................................... 3-40
Branch Prediction ................................................................................................. 3-40
Fixed-Point Processor ............................................................................................... 3-40
MPC565 Reference Manual, REV 2.2
Freescale Semiconductor
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